1. Technical Field
The present invention is directed generally toward a method and apparatus for generating a delay in bus signals. More specifically, the present invention is directed toward a method and apparatus for generating a delay, wherein the delay periods may be easily changed when bus specifications are updated.
2. Description of the Related Art
A typical computer system includes a central processing unit (CPU) for performing computations, memory, and peripheral devices such as display monitors, printers, and disk drives for offline storage and communication with the outside world. Without something to interconnect these components, however, they cannot function as a system.
The primary apparatus for the interconnection of components in a computer system is known as a bus. A bus is a group of signals that allows for communication between devices. A bus is like a data expressway, where the computer system components are positioned at the entrance and exit ramps. For instance, the central processing unit, memory, and peripheral devices may all be connected in parallel to a single bus.
Several different levels of buses may exist in a computer system. At the lowest level is the component-oriented (local) bus, which connects directly to the CPU. Component-oriented buses are generally specific to the particular type of CPU being used. For instance, the component-oriented bus in a computer system built around a Pentium microprocessor (CPU) is incompatible with a PowerPC microprocessor (CPU).
In many computers, however, there are two or more levels of buses (particularly in more modem computer systems). The component-oriented bus is often supplemented with a backplane or system bus. A backplane bus does not interface directly with the CPU, but is connected to the component-oriented bus by means of a backplane-to-host bridge.
Using a backplane bridge has a number of advantages, but two of them are of particular importance. First, because backplane buses are not connected to the component-oriented bus and CPU directly, when a component on the backplane bus fails, there is less likelihood of complete system failure, because the failure is isolated. Second, because backplane buses need not be specific to a particular model of processor, it is possible to have backplane bus standards that are independent of the choice of processor. This allows peripheral devices such as input/output (I/O) adapters to be interchangeable among disparate computing platforms.
One level further out from backplane buses are peripheral bus systems. Peripheral bus systems are true buses, but they are generally accessed through an input/output adapter situation on a backplane bus. Peripheral buses are commonly used to control storage devices, such as floppy disk drives and hard drives. Popular peripheral bus standards include the Small Computer System Interface (SCSI) standard and the Universal Serial Bus (USB) standard.
In all standard bus systems, there are various timing specifications that must be complied with. For example, in the SCSI peripheral bus standard, when one or more devices need to control the bus, a process known as arbitration must take place so that only one device on the bus is allowed to control the bus at any one time. This and other processes within the SCSI standard require the introduction of various delays in the timing of bus signals. Typically, these delays are regulated by custom hardware specifically designed to conform to the bus standard's specifications.
Bus standards, however, are not static entities. They evolve over time. When timing specifications associated with a bus standard change, therefore, hardware designed to conform to the bus standard must be updated to take into account the changes. When custom designed hardware must be redesigned to effect the changes, it can be a very time-consuming process. What is needed, then, is delay-producing circuitry that can be updated without expensive hardware changes.